`timescale 1ns/1ps
//in wrapper ,all control signals active high

module ram_2p_d16384_w256_wrapper (clk,wren,waddr,wdata,rden,raddr,ram_2p_cfg_register,rdata);
  input  clk;
  input  wren;//write enable,active high 
  input [13:0] waddr;//waddr
  input [255:0] wdata;//wdata
  input  rden;//read enable,active high
  input [13:0] raddr;//raddr
  input [9:0] ram_2p_cfg_register;
  output [255:0] rdata;//rdata


wire [63:0] rdata1,rdata2,rdata3,rdata4,rdata5,rdata6,rdata7,rdata8;

wire whigh,rhigh;

wire wren1,wren2;
wire rden1,rden2;


reg [63:0] rdata1_tmp,rdata2_tmp,rdata3_tmp,rdata4_tmp;

reg rden1_ff,rden2_ff;

assign whigh = waddr[13];
assign rhigh = raddr[13];

assign wren1 = wren&&whigh;

assign wren2 = wren&&(~whigh);


assign rden1 = rden&&rhigh;

assign rden2 = rden&&(~rhigh);


assign rdata = {rdata4_tmp,rdata3_tmp,rdata2_tmp,rdata1_tmp};

always @ (posedge clk)
begin 
rden1_ff <= rden1;
rden2_ff <= rden2;
end

always@(*)
begin
if(rden1_ff) begin
rdata1_tmp = rdata1;
rdata2_tmp = rdata2;
rdata3_tmp = rdata3;
rdata4_tmp = rdata4;
end
else if(rden2_ff) begin
rdata1_tmp = rdata5;
rdata2_tmp = rdata6;
rdata3_tmp = rdata7;
rdata4_tmp = rdata8;
end
else begin
rdata1_tmp = 64'b0;
rdata2_tmp = 64'b0;
rdata3_tmp = 64'b0;
rdata4_tmp = 64'b0;
end
end 

ram_2p_d8192_w64 U1_ram_2p_d8192_w64 ( 
.QA(rdata1), 
.CLK(clk), 
.CENA(~rden1),//read enable,active low 
.CENB(~wren1),//write enable,active low
.AA(raddr[12:0]), 
.AB(waddr[12:0]), 
.DB(wdata[63:0]), 
.STOV(ram_2p_cfg_register[9]), 
.STOVAB(ram_2p_cfg_register[8]), 
.EMA(ram_2p_cfg_register[7:5]), 
.EMAW(ram_2p_cfg_register[4:3]),
.EMAS(ram_2p_cfg_register[2]), 
.EMAP(ram_2p_cfg_register[1]), 
.RET1N(ram_2p_cfg_register[0])
);

ram_2p_d8192_w64 U2_ram_2p_d8192_w64 ( 
.QA(rdata2), 
.CLK(clk), 
.CENA(~rden1),//read enable,active low 
.CENB(~wren1),//write enable,active low
.AA(raddr[12:0]), 
.AB(waddr[12:0]), 
.DB(wdata[127:64]), 
.STOV(ram_2p_cfg_register[9]), 
.STOVAB(ram_2p_cfg_register[8]), 
.EMA(ram_2p_cfg_register[7:5]), 
.EMAW(ram_2p_cfg_register[4:3]),
.EMAS(ram_2p_cfg_register[2]), 
.EMAP(ram_2p_cfg_register[1]), 
.RET1N(ram_2p_cfg_register[0])
);
ram_2p_d8192_w64 U3_ram_2p_d8192_w64 ( 
.QA(rdata3), 
.CLK(clk), 
.CENA(~rden1),//read enable,active low 
.CENB(~wren1),//write enable,active low
.AA(raddr[12:0]), 
.AB(waddr[12:0]), 
.DB(wdata[191:128]), 
.STOV(ram_2p_cfg_register[9]), 
.STOVAB(ram_2p_cfg_register[8]), 
.EMA(ram_2p_cfg_register[7:5]), 
.EMAW(ram_2p_cfg_register[4:3]),
.EMAS(ram_2p_cfg_register[2]), 
.EMAP(ram_2p_cfg_register[1]), 
.RET1N(ram_2p_cfg_register[0])
);

ram_2p_d8192_w64 U4_ram_2p_d8192_w64 ( 
.QA(rdata4), 
.CLK(clk), 
.CENA(~rden1),//read enable,active low 
.CENB(~wren1),//write enable,active low
.AA(raddr[12:0]), 
.AB(waddr[12:0]), 
.DB(wdata[255:192]), 
.STOV(ram_2p_cfg_register[9]), 
.STOVAB(ram_2p_cfg_register[8]), 
.EMA(ram_2p_cfg_register[7:5]), 
.EMAW(ram_2p_cfg_register[4:3]),
.EMAS(ram_2p_cfg_register[2]), 
.EMAP(ram_2p_cfg_register[1]), 
.RET1N(ram_2p_cfg_register[0])
);

ram_2p_d8192_w64 U5_ram_2p_d8192_w64 ( 
.QA(rdata5), 
.CLK(clk), 
.CENA(~rden2),//read enable,active low 
.CENB(~wren2),//write enable,active low
.AA(raddr[12:0]), 
.AB(waddr[12:0]), 
.DB(wdata[63:0]), 
.STOV(ram_2p_cfg_register[9]), 
.STOVAB(ram_2p_cfg_register[8]), 
.EMA(ram_2p_cfg_register[7:5]), 
.EMAW(ram_2p_cfg_register[4:3]),
.EMAS(ram_2p_cfg_register[2]), 
.EMAP(ram_2p_cfg_register[1]), 
.RET1N(ram_2p_cfg_register[0])
);

ram_2p_d8192_w64 U6_ram_2p_d8192_w64 ( 
.QA(rdata6), 
.CLK(clk), 
.CENA(~rden2),//read enable,active low 
.CENB(~wren2),//write enable,active low
.AA(raddr[12:0]), 
.AB(waddr[12:0]), 
.DB(wdata[127:64]), 
.STOV(ram_2p_cfg_register[9]), 
.STOVAB(ram_2p_cfg_register[8]), 
.EMA(ram_2p_cfg_register[7:5]), 
.EMAW(ram_2p_cfg_register[4:3]),
.EMAS(ram_2p_cfg_register[2]), 
.EMAP(ram_2p_cfg_register[1]), 
.RET1N(ram_2p_cfg_register[0])
);

ram_2p_d8192_w64 U7_ram_2p_d8192_w64 ( 
.QA(rdata7), 
.CLK(clk), 
.CENA(~rden2),//read enable,active low 
.CENB(~wren2),//write enable,active low
.AA(raddr[12:0]), 
.AB(waddr[12:0]), 
.DB(wdata[191:128]), 
.STOV(ram_2p_cfg_register[9]), 
.STOVAB(ram_2p_cfg_register[8]), 
.EMA(ram_2p_cfg_register[7:5]), 
.EMAW(ram_2p_cfg_register[4:3]),
.EMAS(ram_2p_cfg_register[2]), 
.EMAP(ram_2p_cfg_register[1]), 
.RET1N(ram_2p_cfg_register[0])
);

ram_2p_d8192_w64 U8_ram_2p_d8192_w64 ( 
.QA(rdata8), 
.CLK(clk), 
.CENA(~rden2),//read enable,active low 
.CENB(~wren2),//write enable,active low
.AA(raddr[12:0]), 
.AB(waddr[12:0]), 
.DB(wdata[255:192]), 
.STOV(ram_2p_cfg_register[9]), 
.STOVAB(ram_2p_cfg_register[8]), 
.EMA(ram_2p_cfg_register[7:5]), 
.EMAW(ram_2p_cfg_register[4:3]),
.EMAS(ram_2p_cfg_register[2]), 
.EMAP(ram_2p_cfg_register[1]), 
.RET1N(ram_2p_cfg_register[0])
);
endmodule
